NEC's content addressable memory enables data storage without power usage

NEC recently announced the world’s first content addressable memory (CAM) which will solve many speed issues. CAM can process and retrieve the data while the power is off. CAM can store data on a circuit without using the power because it uses the magnetic substances in reaction to the magnetization to the vertical wall domain elements. This is a huge step towards improving the Networking systems where NEC will change the procedure of data search in high speed searching applications. Now the most exciting fact-it can retrieve the data within five nanoseconds.

Content addressable memory
Content addressable memory

Co developed with Tohoku University, the basis of CAM is the spintronics logic integrated circuit technology where the negative particles of the electrons and the spin magnetic moment are used. The use of CAM with the existing non-volatile memory will result in a greater non-volatility of the central processing units used in storage devices and electronics. The device will start instantly and consume zero electricity while on standby mode. Moreover, the new CAM will share the transistors, reducing the number from eight to three in every two cells, which will reduce the CAM area by 50%.

The growth of cloud computing has resulted in increased use of ICT equipment. Most of the equipments start instantly and the circuits remain active even in standby mode. Therefore, the power consumption by these equipments is a very serious concern and the solution is CAM.

Main features of CAM:

a. Data retrieval speed: Two spintronics devices connected with each other in one cell, spinning in opposite directions connected with each other makes the CAM volatile with high data retrieval speed. This new process also reduces the number of writing switches, which makes CAM more compact.

b. Reduced Circuit Area: The feature of sharing the transistors makes the CAM compact by 50%. The vertical domain wall element can separates the route into reading and writing which reduce the number of transistors by sharing them from eight to three in every two cells.

Via: Physorg

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