The innovations are showing new colors daily. With the emergence of new high-speed technology, an intense hunger for the power consumption is also going up. As all of you know that Intel has made an attempt in the field of power-conservation so that it has recently created new Core 2 microprocessors that eventually eliminates the power consumption. One of the think tanks amongst Intel architects Dileep Bhandarkar puts light on the fresh technical-facts to how hoard the power performance through Core 2 processors.
He educates that Intel has exploited clock frequency so as to increase the processing speed of CPU. Intel accomplished the objective but power consumption went up with high performance (135W in high-performer NetBurst desktop CPU, the Pentium Extreme Edition 3.73GHz dual core CPU).
Reduction in clock frequency can eliminate valuable one cubic power-consumption so that increasing the efficiency of processor with a considerable decrease in power utilization, Bhandarkar said. Widening the microarchitecture is one more alternative commonly used. By issuing four instructions per clock, rather than the previous three, the CPU can realize up to 33% better performance with no increase in clock frequency.
Bhandarkar revealed few more essentials about power management. He told that the Pentium M and Core Duo processors also come with power management ability. Intel CPUs under high load, the inactive parts of the processor remains inactive to reduce power consumption.
Busses are specially designed for worst case transfers. For example, some worst case situations may need to move 16 bytes of data, so the data transfer is 128 bits wide. For maximum performance, you’d want the bus to be able to move that 16 bytes in one clock cycle, so you make the bus 128 bits wide.
CPU contains few other added features like digital thermal sensors and platform environmental control. Manufacturing processes play a vital role to reduce power utilization. Intel is emphasizing silicon technology that reduces wastage of power from transistor by 5x. ‘Sleep transistors’ are good enough to reduce the leakage that is embedded inside the SRAM caches. Imminent 45nm technology is also a landmark in the field of power conservation that will come out by the end of 2007.
Special thanks to Loyd Case
Via: extremetech
